Domino logic circuit techniques have been used in modern high performance microprocessors because of the superior speed and area characteristics of the dynamic circuits as compared to the static CMOS circuits. However, the domino logic gates used in the domino logic circuit typically consume more dynamic switching power and display weaker noise immunity as compared to the static CMOS gates used in the static CMOS circuits. The low power and error free operation of domino logic circuits is a major challenge in the current CMOS technologies.
The domino logic circuits may include: (1) a precharge circuit that pre-charges one or more nodes in the circuit to a predetermined value; (2) a keeper circuit that keeps or maintains the node in the circuit at the predetermined value; (3) an input circuit that inputs one or more signals and that determines the value to output on the output circuit; and (4) an output circuit.
One example of a domino logic circuit is shown in FIG. 1. The domino logic circuit shown in FIG. 1 includes a single power supply and a single ground voltage. Further, the domino logic circuit includes a transistor connected between the pull-down network and ground, thereby making the domino logic circuit “footed.” The pre-charge circuit comprises a pull-up transistor (pull-up). During operation in the precharge phase, the clock signal is low. The dynamic node may thus be charged to the power supply voltage (VDD) by the pull-up transistor. The output node is discharged to the ground voltage (Vgnd) by the output inverter. During operation in the evaluation phase, the clock signal transitions to high. After which, the pull-up transistor is cut-off. In order to maintain the dynamic node at its precharged value, a keeper circuit (keeper) may be used. One example of a keeper circuit, shown as a switch, is illustrated in FIG. 1.
The domino circuit may also include an input circuit, which may include logic for inputting one or more signals and determining the value to output on the output circuit. Any logic may be used for the input circuit including OR, AND, NAND, NOR, XOR, etc. For example, FIG. 1 shows a pull-down network as an input circuit. Depending on the inputs to the pull-down network, the dynamic node is discharged to Vgnd. The domino circuit may further include an output circuit. The output circuit may, at its input, be connected to or in communication with the dynamic mode, and at its output, be connected to the next stage of the circuit. During the evaluation phase, the output node voltage may transition to VDD. The dynamic and output nodes are charged/discharged in every clock cycle provided that the inputs are maintained high. The dynamic switching power consumption of a domino gate is, therefore, higher than a static CMOS gate.
Attempts have been made to reduce the power consumption in domino logic circuits. FIG. 2 shows one example of a low swing circuit technique attempting to reduce the power consumption in domino logic circuits. The circuit depicted in FIG. 2 reduces the voltage swing at the output while maintaining a full voltage swing signal at the dynamic node of a domino gate. As shown in FIG. 2, the domino logic circuit relies on an additional capacitor C1 to stabilize the reference voltage; however, this design significantly increases the circuit area. Others have attempted similar low swing domino circuits that suffer from a variety of problems including degraded evaluation speeds and in achieving a smaller area overhead. Further, the power-delay product (PDP) issue is not addressed.
FIG. 3 shows another example of a dynamic node low swing domino circuit with single power supply and ground voltage. As shown in FIG. 3, the circuit utilizes NMOS and PMOS transistors to reduce and increase, respectively, the upper and lower boundary of the voltage swing at the dynamic node. Although the dynamic switching power is reduced, the output inverter is always simultaneously turned on, thereby producing significant short-circuit current. Since the pull-up and pull-down transistors are simultaneously activated in the output inverter, the output voltage swing is degraded. Similarly, the evaluation speed is significantly reduced. Therefore, what is needed is a low swing domino logic circuit that reduces power consumption without suffering the drawbacks of prior low swing circuits.